Regviz

NXP Semiconductors /LPC18xx /RGU /RESET_CTRL1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RESET_CTRL1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC18xx/RGU/RESET_CTRL1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIMER0_RST)TIMER0_RST 0 (TIMER1_RST)TIMER1_RST 0 (TIMER2_RST)TIMER2_RST 0 (TIMER3_RST)TIMER3_RST 0 (RITIMER_RST)RITIMER_RST 0 (SCT_RST)SCT_RST 0 (MOTOCONPWM_RST)MOTOCONPWM_RST 0 (QEI_RST)QEI_RST 0 (ADC0_RST)ADC0_RST 0 (ADC1_RST)ADC1_RST 0 (DAC_RST)DAC_RST 0 (RESERVED)RESERVED 0 (UART0_RST)UART0_RST 0 (UART1_RST)UART1_RST 0 (UART2_RST)UART2_RST 0 (UART3_RST)UART3_RST 0 (I2C0_RST)I2C0_RST 0 (I2C1_RST)I2C1_RST 0 (SSP0_RST)SSP0_RST 0 (SSP1_RST)SSP1_RST 0 (I2S_RST)I2S_RST 0 (SPIFI_RST)SPIFI_RST 0 (CAN1_RST)CAN1_RST 0 (CAN0_RST)CAN0_RST 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED 0 (RESERVED)RESERVED

Description

Reset control register 1

Fields

TIMER0_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
TIMER1_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
TIMER2_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
TIMER3_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
RITIMER_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
SCT_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
MOTOCONPWM_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
QEI_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
ADC0_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
ADC1_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
DAC_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
RESERVED

Reserved
UART0_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
UART1_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
UART2_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
UART3_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
I2C0_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
I2C1_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
SSP0_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
SSP1_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
I2S_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
SPIFI_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
CAN1_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
CAN0_RST

Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle.
RESERVED

Reserved.
RESERVED

Reserved
RESERVED

Reserved.
RESERVED

Reserved
RESERVED

Reserved
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data